Senior Digital Design Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8c9nae

Overview
As Senior Digital IC Designer at NXP in Milan, you will drive RTL design and digital integration for automotive and industrial electrification.
You will partner with architects, verification engineers, and cross-functional teams to balance performance, power, area, and safety.
You will contribute to reusable IP, mixed-signal collaboration, and silicon bring-up to deliver robust digital subsystems.
This role offers impact on automotive-grade mixed-signal products and cutting-edge power-management solutions.
Retribuzione / Benefits
competitive benefits package
annual incentive opportunities
equity
remuneration aligned with national agreement
opportunities for professional growth
global collaboration across sites
Responsabilità
Develop RTL designs for complex digital blocks and subsystems using SystemVerilog/Verilog
Contribute to digital architecture definition with senior designers and system architects
Analyze design trade-offs for performance, power, area, safety, and testability
Implement robust clocking, reset, and power management strategies
Support IP integration and subsystem-level development
Perform RTL verification activities (simulation, lint, CDC, synthesis checks) with verification engineers
Support timing closure and implementation activities




Participate in design reviews and sign-off readiness
Support silicon bring-up, debugging, characterization, and root-cause analysis
Work within mixed-signal project teams and promote reuse of digital IPs and design methodologies
Contribute to safety mechanisms in line with automotive standards and support ISO ***** concepts
Requisiti fondamentali
Master's degree in Electrical Engineering, Electronics Engineering, or equivalent
Minimum 7 years of experience in digital IC design
Strong experience in RTL development using SystemVerilog/Verilog
Experience with synthesis, timing constraints, and digital implementation flows
Understanding of CDC, reset strategies, and low-power design concepts
Familiarity with DFT fundamentals and design-for-test methodologies
Experience working in mixed-signal IC development environments
Knowledge of digital verification methodologies and simulation-based verification
Experience with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA)
Fluent written and spoken English
Cross-functional collaboration
Mentoring and knowledge sharing
Strong problem-solving and debugging
SystemVerilog/Verilog RTL
Synthesis and timing constraints
Digital implementation flows

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8c9nae