Senior Analog IC Layout Engineer - MCU

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8cgb87

h3Role Summary /h3pThe Senior Layout Engineer is a highly skilled technical contributor responsible for the physical implementation of complex analog, mixed-signal, and custom IC designs. Working with a high degree of independence, this role drives layout execution from floorplanning through tape‑out, ensuring that performance, quality, reliability, and schedule objectives are achieved. The position requires strong expertise in advanced layout methodologies, excellent problem‑solving capabilities, and effective collaboration with design, verification, and technology teams. In addition to delivering critical project milestones, the engineer provides technical guidance to less experienced engineers, contributes to methodology improvements, and plays a key role in mitigating project risks and supporting successful silicon delivery. /ph3Key Responsibilities /h3ulliLead the layout implementation of complex analog, mixed-signal, and custom digital blocks. /liliDrive floorplanning, device matching, routing strategies, and layout optimization to meet performance, area, power, reliability, and manufacturability requirements. /liliPerform and review physical verification activities, including DRC, LVS, ERC, EM/IR, latch‑up, density, and reliability checks. /liliCollaborate closely with design, verification, technology, and product engineering teams to resolve layout‑related challenges and achieve project milestones. /liliSupport advanced‑node technologies, including FinFET processes, and contribute to methodology improvements and best practices.



/liliProvide technical guidance and mentorship to junior engineers and contractors. /liliAssess project risks, estimate layout effort, and drive execution to meet aggressive schedules. /li /ulh3Expected Competencies /h3ulliStrong expertise in analog layout techniques, matching, shielding, noise isolation, ESD‑aware layout, power distribution, and high‑performance routing. /liliExcellent understanding of semiconductor process technologies, including planar and FinFET nodes. /liliProficiency with industry‑standard EDA tools and physical verification flows. /liliAbility to independently make technical trade‑offs and solve complex implementation issues. /liliStrong communication and stakeholder management skills. /liliProven track record of successful tape‑outs and delivery of high‑quality silicon. /li /ulh3Impact and Leadership /h3ulliRecognized technical expert within the layout organization. /liliInfluences project execution and physical design methodologies across multiple programs. /liliContributes to organizational capability growth through mentoring, reviews, and knowledge sharing. /liliPlays a key role in achieving project schedules and silicon quality targets. /li /ulh3Qualifications /h3ulliBSEE or MSEE.



/liliApproximately 8‑12+ years of custom analog/mixed‑signal layout experience in deep sub‑micron CMOS. /liliExpert in Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, and PVS DRC/LVS/ERC. /liliStrong knowledge of matching, common centroid, shielding, EM/IR, high‑speed routing, parasitics, and DFM practices. /liliProven experience leading analog‑on‑top and digital‑on‑top chip layouts. /liliExperience with floorplanning, power distribution, ESD, and multiple voltage domains. /liliFamiliarity with PLL, OSC, ADC, DAC, LDO, Bandgap, and high‑speed interface circuits. /liliExcellent communication and cross‑functional leadership skills. /liliFluent in English. /liliSKILL or Perl scripting is a plus. /li /ulpNXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices. As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package. More information about NXP in Italy... /p #J-18808-Ljbffr

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8cgb87