11 ott - Pavia
Exelero
Job description:
- Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products
- Define digital subsystem architectures
- Lead RTL development and integration
- Drive design reviews and quality standards
- Support verification and implementation teams
- Mentor design engineers
Profile description:
- MSc or PhD in Electrical Engineering
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