Senior Analog RFIC Design Engineer

12 ott - Italia
HUAWEI TECHNOLOGIES ITALIA

About Huawei
Huawei is a leading global provider of information and communications technology (ICT) infrastructure and smart devices. With integrated solutions across four key domains – telecom networks, IT, smart devices, and cloud services, we are committed to bringing digital to every person, home and organization for a fully connected, intelligent world.
At Huawei, innovation focuses on customer needs. We have more than 200,000 employees , of which 55% are employed in R&D; , and we operate in more than 170 countries and regions.
Huawei invests more than 20% of revenues in R&D; every year: in the past 10 years our total R&D; investments exceed 150B USD .
By the end of 2025, Huawei held +150.000 active patents .
Our motto is "make it possible", we use our customer-centric obsession, our perseverance, our dedication and a continuous self-challenge to accomplish the most challenging goals and always raise the bar
We are obsessed about continuous improvement and about creating value for the company, for the employees and for society.
We are a place where "results talk and ideas walk",



good ideas are always welcome, but you have to take ownership and make them happen too.
Openness and flexibility are our mantra.
Huawei Milan Research Center is looking for an Analog RFIC Design Engineer who will be responsible for supporting the study, design and development activities of integrated circuits.
You will work in a fast-paced international team engaged in state of the art research and innovation.
If you are enthusiastic in facing new challenges and in top-notch technologies, have a further look
Design of high-performance Analog ICs applied to integrated optical transceiver modules, including simulation, design, verification and optimization
Analyze technical requirement specifications and define target product performance by collaborating with system engineers
Drive and support layout activity for the physical design of building blocks and top levels
Contribute to feasibility

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