DESIGNER ARCHITECT
Pubblicato il 13-10-2026 - Qualcomm in Italia
Company Qualcomm Europe, Inc. Italy Branch Office Job Area CPU Engineering General Summary Qualcomm is a company of inventors that unlocked 5 G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5 Gs potential into world-changing technologies and products. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Explore high performance strategies working with the CPU modeling team.
From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy.
Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery.
Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsys