Senior ams dv engineer
Pubblicato il 13-10-2026 - Analog Devices in Italia
About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible.
Learn more at and on Linked In and X. Senior AMS DV Engineer Custom Silicon Solutions Group The Group: The charter of ADI's CSS team is to lead the market in several technology domains with highly differentiated sensing and signal processing solutions. Today these technology areas include Capacitive Sensing, Optical Image Stabilization, Optical sensing, Audio, Capacitance or Laser Driving, and Power, which drive growth in our portable Consumer business.
With a goal to deliver sustainable growth the CSS group will present the successful candidate with a great opportunity for continuous career development as part of a highly motivated and supportive team. The Position: The group is seeking an experienced Senior AMS Design Verification Engineer to work on the development of new product solutions for portable consumer applications, engaging directly with our Tier 1 OEMs, along with supervisor/mentor leadership opportunities.
Responsibilities
Acting as a mixed signal verification team member in a multi-disciplinary (Digital/Analog/DV/Implementation/Layout) multi-site development team Contribute towards verification strategy and methodology improvement Understand device requirements and come up with traceable AMS verification plan Code/generate SVRNM models of required analog blocks and validate against schematic.
Develop directed tests in AMS environment or reuse constrained random UVM testcases File and track bugs to closure in Jira Document r