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CPU Micro-architect/RTL Designer

Pubblicato il 14-10-2026 - QUALCOMM in Roma

Company: Qualcomm Europe, Inc. Italy Branch Office
Job Area: Engineering Group, Engineering Group > CPU Engineering
Roles and Responsibilities
- Performance exploration. Explore high performance strategies working with the CPU modeling team.
- Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.
- RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
- Functional verification support. Help the design verification team execute on the functional verification strategy.
- Performance verification support. Help verify that the RTL design meets the performance goals.
- Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability.

Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration,



or related work experience.
- Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field.

Preferred Qualifications
- Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems
- Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
- Knowledge of logic design principles along with timing and power implications
- Understanding of low power microarchitecture techniques
- Understanding of high performance techniques and trade-offs in a CPU microarchitecture
- Experience usi

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