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Openchip & Software Technologies
h3The Role /h3 pAs a bSenior /b bFunctional Verification Engineer, /b you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support. /p h3Key Responsibilities /h3 ul liReading and analysing the system requirements and architecture requirement documents. /li liDeveloping Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage. /li liExecuting Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures. /li liUsing the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, …). /li liCreate and execute testcases to verify the functionality, performance, and robustness in embedded C and SV. /li liIdentify, isolate,
and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams. /li liWork closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities. /li liParticipation to verification methodology improvements. /li liOrganize work and deliverables between skills, internal and external teams. /li liOpportunities for mentoring and training the next generation of verification engineers. /li /ul h3Qualifications /h3 ul liMaster Degree in relevant field. /li liMin 7 years of experience in relevant field of Verification of complex SoC or IP. /li liExperience in /li liSystemVerilog/UVM /li liSystemC/C++ /li liExperience in Constrained random, Functional Coverage development, desi
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