Senior Digital Design Engineer for MEMs ASIC
Pubblicato il 15-10-2026 - Analog Devices in Pavia
Senior Digital Design Engineer for MEMs ASICApply: Italy, Milan, Assago: Tempo pieno: Posted Today: R266098About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn and on LinkedIn and X.Senior Digital Design Engineer About the Role As a Senior Digital Design Engineer, you will lead block-level designs and verification efforts. You'll be responsible for complex digital systems, timing closure, and power optimization while mentoring junior engineers.
This position requires deep understanding of digital design methodologies and the ability to interact with customers to gather requirements and provide technical solutions. Key Responsibilities* Lead block-level digital designs and verification activities* Develop and implement complex digital systems with focus on performance optimization* Ensure timing closure and power optimization for critical design blocks* Mentor junior engineers and provide technical guidance* Interface with customers to understand requirements and present technical solutions* Drive cross-functional collaboration to ensure cohesive system designMust Have Skills* Digital Circuit Design: Advanced expertise in complex digital circuit design and implementation* Timing Closure: Strong capability in achieving timing closure on complex designs* Power Optimization: Practical experience optimizing digital designs for power efficiency* Mixed-Signal Integration: Ability to integrate digital blocks with analog/mixed-signal environments* Digital Architecture: Competence in block-level ar