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SerDes System Design Engineer

Pubblicato il 16-10-2026 - Synopsys in Pavia

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent your academic career and early professional years building an understanding on different aspects of either analog or digital design and have curiosity of how high-speed communication systems actually work, not just in theory but in the messy reality where channel loss, jitter, non linearities, DSP sizing, LMS convergence and impedance mismatches determine whether a link closes or fails. You strive for holistic understanding of complex systems and you believe the way to create at optimized product is to capture the interaction between analog circuits, digital logic, and algorithms in a single coherent simulation environment.





Collaboration comes naturally to you.

When a model behaves differently than the circuit description suggests you hunt for the truth. You sit with the analog designer who owns the amplifier block, understand the frequency response trade-offs, and update your MATLAB representation until it reflects reality. You are comfortable presenting technical results in gate reviews and defending your sign-off decisions when someone questions your assumptions.

You care about closing the loop between simulation and silicon. When lab measurements do not match your predictions, you treat it as a puzzle and get into the lab to solve it. At Synopsys, you will work on leading edge SerDes IP that powers PCIe and Ethernet interfaces across the semiconductor industry.

What You'll Be Doing
- Build and update MATLAB models of SerDes analog and DSP blocks in cooperation with the system architect, translating circuit d

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