Senior Analog IC Layout Engineer
Pubblicato il 16-10-2026 - NXP Semiconductors in Lodi
Role Summary The Senior Layout Engineer is a highly skilled technical contributor responsible for the physical implementation of complex analog, mixed-signal, and custom IC designs. Working with a high degree of independence, this role drives layout execution from floorplanning through tape-out, ensuring that performance, quality, reliability, and schedule objectives are achieved. The position requires strong expertise in advanced layout methodologies, excellent problem-solving capabilities, and effective collaboration with design, verification, and technology teams. In addition to delivering critical project milestones, the engineer provides technical guidance to less experienced engineers, contributes to methodology improvements, and plays a key role in mitigating project risks and supporting successful silicon delivery. Key Responsibilities * Lead the layout implementation of complex analog, mixed-signal, and custom digital blocks. * Drive floorplanning, device matching, routing strategies, and layout optimization to meet performance, area, power, reliability,
and manufacturability requirements. * Perform and review physical verification activities, including DRC, LVS, ERC, EM/IR, latch-up, density, and reliability checks. * Collaborate closely with design, verification, technology, and product engineering teams to resolve layout-related challenges and achieve project milestones. * Support advanced-node technologies, including FinFET processes, and contribute to methodology improvements and best practices. * Provide technical guidance and mentorship to junior engineers and contractors. * Assess project risks, estimate layout effort, and drive execution to meet aggressive schedules. Expected Competencies * Strong expertise in analog layout techniques, matching, shielding, noise isolation, ESD-aware layout, power distribution, and high-performance routing. * Excellent understanding of semiconductor process technologies, including planar and FinFET nodes. * Proficie