Sr. ASIC Design Engineer
Pubblicato il 17-10-2026 - VisLab (an Ambarella Inc. in Parma
We’re growing Our team in Parma (Italy) is seeking a Sr. ASIC Design Engineer.
Responsibilities:
- Developing micro-architecture specifications for a next generation Computer Vision processor;
- Designing and implementing Verilog/SytemVerilog modules for cutting edge SOCs. Examples of such modules include:
- Image processing logic
- Vector processors
- Device / Memory controllers
- Design integration, logic synthesis, and design optimization for timing, area and power;
- Developing front-end methodologies and tool flows;
Requirements:
- Master’s degree in Electrical Engineering with 0-4 years of experience;
- Very good understanding of VLSI/ASIC design, Computer architecture and Logic design;
- Good knowledge and experience in using hardware description languages (Verilog/SystemVerilog);
- Ability to program in scripting languages,
like Python and Perl;
- Knowledge of design verification, and functional coverage;
- Strong communication skills and a good team player;
- Knowledge of logic synthesis and timing closure is a must
- Knowledge and/or experience in the areas of Image/Video processing, computer vision, machine learning are plus;
As an Equal Opportunity/Affirmative Action Employer, Vislab and Ambarella recruit qualified applicants without regard to race, color, national origin, sex, physical disability, or veteran status.
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