Cad & Eda Flow Engineer
Pubblicato il 15-10-2026 - Fondazione Chips-IT in Pavia
About Fondazione Chips-IT
The Foundation "Italian Center for the Design of Semiconductor Integrated Circuits," also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.
The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
Promote the design and development of integrated circuits
Strengthen the system of professional training in the field of microelectronics
Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field
Posizione
We are seeking a
About Fondazione Chips-IT
The Foundation "Italian Center for the Design of Semiconductor Integrated Circuits," also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.
The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
Missions Of The Foundation
Promote the design and development of integrated circuits
Strengthen the system of professional training in the field of microelectronics
Ensure the establishment of a network of universities,
research centers and enterprises that fosters innovation and technology transfer in the field
Posizione
We are seeking a CAD & EDA Flow Engineer to manage, optimize, and maintain our Electronic Design Automation (EDA) infrastructure. In this role, you will serve as the technical backbone for our R&D; teams, managing relationships with EDA vendors and foundries, and ensuring smooth PDK integration for advanced SoC design up to tape-out. The work can be carried out either in Pavia or in Bologna.
Key Responsibilities
Manage EDA tool procurement, licenses, and vendor relationships (Cadence, Synopsys, Siemens).
Install, configure, and maintain Process Design Kits (PDKs) across all design workflows (digital, analog and RF).
Act as the primary technical liaison with foundries for PDK installation and maintenance, design rule checks (DRC/LVS), and issue resolution.
Maintain and optimize EDA toolchains for synthesis, simulation, verification, and physical implementation. Experience on emulation systems is a plus.
Create and update internal trainings, technical documentation, scripts, and best practices for internal design teams.
Requisiti
Master's degree in Electrical/Computer Engineering or Microelectronics.
Proven experience in EDA tool administration and PDK management (Cadence, Synopsys, Siemens).
Good knowledge of semiconductor fabrication flows and foundry interfaces.
Familiarity with scripting languages (Tcl, Python, Bash) for design flow automation.
Basic understanding of HDL languages (Verilog, SystemVerilog, VHDL).
Experience with advanced process nodes is considered a strong plus.
Altre Informazioni
WHAT WE OFFER:
Competitive compensation and contract type, to be negotiated based on qualifications and experience
Possibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.
Lunch tickets
Private health care coverage depending on your role and contract
Structured growth path, with ongoing access to training and updates
Networking opportunities with industry-leading professionals
International environment
Hybrid work policy
Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years
In conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro ******,00 e ******,00. L'ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all'effettiva esperienza e alle competenze del candidato, e sarà integrata dai vantaggi aziendali previsti per il ruolo.