Senior ASIC Design Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8i2tnn

VisLab (an Ambarella Inc.

Si assicuri di leggere attentamente le informazioni relative a questa occasione prima di inviare la sua candidatura.

company) in Parma, Italy seeks a Sr.

ASIC Design Engineer to develop micro‑architecture for a next‑gen computer vision processor and implement modules in Verilog/SystemVerilog for SOCs.
You will optimize timing, area and power while advancing front‑end methodologies and tool flows. xysqume

The role requires a Master’s in Electrical Engineering and 0–4 years of relevant experience with strong HDL skills and scripting ability in Python or Perl.

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8i2tnn