Senior Staff Engineer Radio Frequency Design

19 ott - Veneto
Infineon Technologies

Join our international RF and mixed-signal design team and drive the development of next-generation Frequency Synthesizers for cutting-edge semiconductor solutions. In this role, you will combine deep analog and RF expertise with digital-assisted design approaches, working closely with system architects, digital designers and validation experts from concept to silicon. Your roleKey responsibilities in your new rolePLL Concept & Architecture: Define and evaluate RF Digital PLL concepts (e.g., Fractional-N, ADPLL, Sub-sampling PLLs) and architectures tailored for high-frequency wireless applicationsModeling & Noise Budgets: Develop high-level behavioral models (e.g., MATLAB, Simulink, Verilog-A) to analyze and optimize RF PLL loop dynamics, jitter, spurs, and stringent phase noise performance. Circuit Design & Implementation: Translate concepts into high-performance RF and mixed-signal circuits, focusing on critical blocks such as VCOs/DCOs, high-speed frequency dividers (prescalers), Phase-Frequency Detectors, and Charge Pumps, TDC, DTCDigitally-Assisted RF Calibration:



Architect and verify digital calibration algorithms for PLL (e.g., spur mitigation, and mismatch compensation, TDC, DTC calibrations) to enhance RF performanceSystem Partitioning: Partner closely with system architects, digital, and RF frontend teams to optimize mixed-signal and RF system partitioning for transceiver architecturesLayout & Silicon Characterization: Guide layout engineers to preserve RF signal integrity, minimize parasitic effects, and ensure optimal isolation. Support laboratory validation teams during silicon characterization and debugging of the RF PLLYour profileQualifications and skills to help you succeedEducation: A degree (Master/PhD preferred) in Electrical Engineering, Microelectronics, or a related field with a focus on RF/microwave designExperience: 5+ years of proven experience specifically focused on RF Digital PLL concept definition, architectural modeling, and circuit de

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