Principal HS Digital Design Engineer (d/m/f)

23 ott - Pavia
Appcast

Your tasks

Scopra di più sui compiti quotidiani, le responsabilità generali e l'esperienza richiesta per questa possibilità scorrendo subito verso il basso.

- Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products
- Define digital subsystem architectures
- Lead RTL development and integration
- Drive design reviews and quality standards
- Support verification and implementation teams
- Mentor design engineers

Who we are looking for

- MSc or PhD in Electrical Engineering
- 10+ years digital IC design experience
- RTL design (Verilog/SystemVerilog)
- High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe,



PCIe or similar protocols is an advantage
- Interface protocols and clock-domain crossing
- Synthesis and timing analysis
- Advanced CMOS node experience, including FinFET and/or FD-SOI, is required ams OSRAM is an Equal Employment Opportunity Employer. Diversity, equity and inclusion is strongly established in our corporate culture and we firmly believe it makes us more successful as a company. xysqume All qualified applications will receive consideration for employment regardless of ethnic, national or social origin, gender, gender identity, sexual orientation, color, religion, age, physical and mental abilities.

Digital, Media

25 ott - Casalecchio di Reno
Artemest

EMEA Private Client Experience

25 ott - Pavia
Lvmh

Ricevi nuove offerte di lavoro

Crea una Job Alert gratuita per principal hs digital design engineer (d/m/f) / pavia

Field Application Engineer – Macchine Utensili

25 ott - Rovigo
CarusiHR Srl Unipersonale

Driveline Test Engineer: Lab

25 ott - Reggio Emilia
Groupe SEGULA Technologies SA (old)