24 ott - La Spezia
Nokia
Nokia seeks an experienced ASIC physical design engineer to implement floorplanning, place & route, and power/clock distribution for submicron nodes. You will work with a hardware/RTL team to translate designs into silicon and optimize flows.
This role emphasizes collaboration across cross-functional teams, verification rigor, and automation, with hybrid work and strong learning opportunities in latest nodes and tools.
#J-18808-Ljbffr
25 ott - Cesano Boscone
Alten Group
25 ott - Campodoro
Sanmarco Informatica
25 ott - Orta di Atella
Adecco Italia
25 ott - Volpiano
Exprivia