Principal HS Digital Design Engineer (d/m/f)

25 ott - Pavia
Ams Italy

Your tasksbr/br/Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products Define digital subsystem architectures Lead RTL development and integration Drive design reviews and quality standards Support verification and implementation teams Mentor design engineersbr/br/Who we are looking forbr/br/MSc or PhD in Electrical Engineering 10+ years digital IC design experience RTL design (Verilog/SystemVerilog) High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe,



PCIe or similar protocols is an advantage Interface protocols and clock-domain crossing Synthesis and timing analysis Advanced CMOS node experience, including FinFET and/or FD-SOI, is requiredbr/br/ams OSRAM is an Equal Employment Opportunity Employer. Diversity, equity and inclusion is strongly established in our corporate culture and we firmly believe it makes us more successful as a company. All qualified applications will receive consideration for employment regardless of ethnic, national or social origin, gender, gender identity, sexual orientation, color, religion, age, physical and mental abilities.br/br/

Facchino - Hotel 5 Stelle Lusso - €20.000 - €23.000 All'Anno

27 ott - Milano
Adecco

MAGAZZINIERE/A ADDETTO/A ALLA LOGISTICA (RIF. offerta: 88899)

27 ott - San Michele al Tagliamento
During S.p.A. Filiale di Pordenone (PN)

Ricevi nuove offerte di lavoro

Crea una Job Alert gratuita per principal hs digital design engineer (d/m/f) / pavia

OPERAIO/A GENERICO/A CAT PROT/99

27 ott - Rivignano
Lavoropiù

Operatore/operatrice fiscale

27 ott - Italia
Adecco