26 ott - Pavia
Ams Italy
Your tasksTechnical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC productsDefine digital subsystem architecturesLead RTL development and integrationDrive design reviews and quality standardsSupport verification and implementation teamsMentor design engineersWho we are looking forMSc or PhD in Electrical Engineering10+ years digital IC design experienceRTL design (Verilog/SystemVerilog)High-speed digital IC design
27 ott - Milano
Adecco
27 ott - San Michele al Tagliamento
During S.p.A. Filiale di Pordenone (PN)
27 ott - Rivignano
Lavoropiù
27 ott - Italia
Adecco