Senior Engineer – Silicon-to-System Power Delivery & Integrity

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h3About Huawei /h3pHuawei is a leading global provider of information and communications technology (ICT) infrastructure and smart devices. With integrated solutions across four key domains – telecom networks, IT, smart devices, and cloud services, we are committed to bringing digital to every person, home and organization for a fully connected, intelligent world. At Huawei, innovation focuses on customer needs. We invest heavily in basic research, concentrating on technological breakthroughs that drive the world forward. We have more than b200,000 employees /b, of which b55% are employed in RD /b, and we operate in more than 170 countries and regions. Huawei invests more than b20% of revenues in RD /b every year: in the past 10 years our total bRD investments exceed 150B USD /b. By the end of 2025, Huawei held b+150.000 active patents /b. Central Hardware Engineering Institute (CHEI) at bHuawei Milan Research Center /b focuses on advanced hardware technologies for next-generation ICT systems, with strong emphasis on high-speed interconnects, power integrity (PI), signal integrity (SI), and system-level performance optimization. The team develops both engineering solutions and internal methodologies/tools to enable robust, scalable hardware design. /ph3We are looking for a: /h3h3Senior Engineer – Silicon-to-System Power Delivery Integrity /h3h3The opportunity /h3pYou will lead research and methodology development in power delivery and power integrity, focusing on the interactions between SoC silicon power characteristics and package to board power delivery architectures. This role centers on developing custom modeling methodologies, computational frameworks and cross-layer optimization strategies to address SoC power delivery challenges in next generation high performance computing platforms. /ph3Key Responsibilities /h3ulliSoC Power Characterization: Research and analyze silicon power characteristics, dynamic current profiles and voltage droop budgets to define target impedance and guide board level design. /liliDie to System PDN Modeling:



Develop and apply advanced PDN/PI modeling methodologies that incorporate silicon power delivery characteristics and transient load behavior to evaluate voltage regulation, die-package-board resonances and opportunities for system-level architectural improvements. /liliSoC Workload-Driven Optimization: Define and optimize board-level PDN architectures, decoupling strategies, and VRM design based on SoC workload characteristics, balancing PI performance, design margins, PCB area, and cost. /liliChip to system framework research: Develop and validate computational frameworks integrating SoC load behavior with system level PDN models, and investigate emerging power delivery technologies to identify feasible research directions and architectural improvement /li /ulh3Required Qualifications /h3ulliM.S. with 6+ years’ industry experience or Ph.D. with 3+ years’ industry experience in Electrical Engineering, (or a related field) with background on system-level PI/PDN design. /liliStrong understanding of Silicon to system power architecture, including SoC power characteristics, transient current behavior, voltage drop constraints and their impact on package and board level PDN design. /liliExperience developing PI methodologies, PDN models, transient analysis workflows and lab correlation. /liliProficiency with industry-standard simulation tools and scripting languages for custom modeling and design automation /li /ulh3Nice to have /h3ulliExperience with AI, HPC or datacenter platforms involving high power density and large transient current demands. /liliFamiliarity with SoC power management techniques, including dynamic voltage and frequency scaling. /liliKnowledge of integrated voltage regulators architectures (IVRs),



high frequency VRMs, advance power delivery architectures and high bandwidth power delivery control loops. /liliExperience developing or validating chip/package/board electrical models and applying computational methods to automate system-level PI. /li /ulh3What We Offer /h3pWe offer you an exciting professional career in one of the leading and fastest growing multinational telecommunication companies, challenging work and a competitive salary package. Personal development is ensured through many training opportunities in Western Europe and abroad. /ppWe offer a gross annual salary typically ranging from €65,000 to €80,000 determined according to objective criteria such as professional experience, competencies, and seniority. Employees may also be considered for a discretionary annual premio ranging from 0 to 2 monthly salaries, subject to company evaluation. The applicable collective bargaining agreement is the CCNL Telecommunications, within levels 6° and 7°. /ph3Privacy Statement /h3pWe therefore commit to protecting your privacy following the local legal data privacy legislation. Please read and understand our West European Recruitment Privacy Notice before submitting your personal data to Huawei so that you fully understand how we process and manage your personal data received ( /ppIf you have any queries in regards to Huawei WEU Data Privacy please feel free to contact our WEU Data Protection Officer by clicking here ( /ppHuawei is an Equal Opportunity Employer and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, genetic information, or any other legally protected status. All qualified applicants will receive consideration for employment without regard to these characteristics. We are committed to creating an inclusive and diverse workplace /ph3Company Info /h3pHuawei Technologies Italia S.r.l. /ppRegistered Office: Via Lorenteggio 240, Tower A, Milan /ppRD Office address: Viale Martesana 12, 20055 Vimodrone (MI) /p #J-18808-Ljbffr

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8nlb2z