Python Engineer
Pubblicato il 26-10-2026 - STMicro in Italia
At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today. When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world. Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential. Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you. We are looking for a talented engineer to join our AMS Verification team and contribute to the functional verification of advanced mixed‑signal ASICs for applications including PMICs, wireless charging, battery charging, display drivers, and other complex integrated solutions. In this role, you will collaborate closely with analog, digital, and system‑level designers to develop and validate high‑quality behavioral models and System Verilog real‑number models used in AMS and DMS verification flows. You will work on models that may be hierarchical or flat, as well as black‑box or white‑box, depending on the verification needs and project phase. Preparing and configuring mixed‑signal simulation environments based on technical documentation Validating outcomes in close cooperation with analog and digital design teams Producing clear, structured technical documentation to present results, assumptions, and conclusions Master’s degree in Electrical, Electronic,
or Computer Engineering Strong ability to understand the architecture and behaviour of complex electronic systems Strong collaboration skills and a proactive attitude Experience with System Verilog real‑number modelling is highly valued Familiarity with mixed‑signal simulation platforms such as: Knowledge of VHDL, Verilog, Verilog‑AMS, or System Verilog is a plus This role is ideal for someone who thrives in a technical, high‑impact environment and is motivated by the opportunity to shape the verification of next‑generation mixed‑signal products. The expected salary range for this position is €37500
- €42000 gross annual salary (RAL), plus variable pay relevant for the role. In accordance with the EU Pay Transparency Directive and applicable Italian legislation, this compensation range has been determined based on objective, gender‑neutral criteria, including job responsibilities, required skills, relevant experience, qualifications, and market benchmarks. Placement within the range will depend on the candidate’s profile and demonstrated competencies. The final offer will be made in compliance with the applicable National Collective Bargaining Agreement (CCNL), where relevant, and our internal compensation policies. We are committed to equal pay for equal work and equal opportunities for all candidates. ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance. At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture. To discover more, visit st.