Lead of Silicon Design Support Infrastructure
Pubblicato il 27-10-2026 - Fondazione Chips-IT in Località Vignazza
pFondazione Chips-IT is seeking a Lead of Silicon Design Support Infrastructure to establish and lead the Design, Validation and Test Infrastructure Group. This Group will enable multi-domain semiconductor demonstrator development (Digital, Analog, Power) supporting internal research teams and collaborations with university and industry partners. /p pThe Group will have a central role in the operation of Chips-IT, providing the best possible environment for Research Groups to develop their projects. Its capabilities should bring the Foundation to demonstration levels of TRL 5 to 7 depending on the projects, while also providing infrastructure access for academic and industrial partners within established collaboration frameworks. /p pThe work can be carried out either in Pavia or in Bologna. /p h3KEY RESPONSIBILITIES /h3 h3Set-Up of the Group /h3 ul liIn coordination with the Research Groups Directors, will define and propose to the CEO the organisation of the Silicon Infrastructure Group and present a 3-year budget forecast /li liTogether with the HR Manager, will define the profiles of the personnel, engineers and technicians, to recruit (initially between 5 and 10 people) /li liIt is expected that the infrastructure will provide the following: /li /ul ol liEDA Tool Management: Installing, maintaining, and upgrading EDA software licenses from vendors like Synopsys, Cadence, Siemens, and Keysight for digital, analog, mixed-signal, and power IC design /li liComputing Infrastructure Optimization: Managing computing environments, including compute clusters, storage, and networking, to support compute-intensive design and simulation workloads across digital, analog, and power domains /li liWorkflow Automation: Continuously developing and optimizing multi-domain design workflows from architecture through tape-out,
using advanced tools and techniques to enable efficient silicon demonstrator development /li liAdvanced Design Tools: Evaluating and enabling cutting-edge design automation tools and methodologies across all semiconductor domains to accelerate development cycles and enhance design quality /li liEmulation and Pre-Silicon Validation: Providing emulation infrastructure for digital designs and supporting hardware-software co-design for demonstrators /li liMulti-Domain Test Facility: Providing comprehensive test capabilities across digital, analog, and power domains including: ul liSilicon characterization for digital, analog, and mixed-signal ICs /li liPower electronics validation (power analyzers, high-voltage benches, thermal characterization /li liRF/analog measurement infrastructure (network/spectrum analyzers, precision equipment) /li liLab automation and safety compliance for all test domains /li liFoundry and Fabrication Coordination: Managing foundry relationships, PDK installations, tape-out scheduling, shuttle run organization, and post-silicon debug support across all technology domains /li /ul /li /ol h3Management of the Group /h3 ul liLicensing and Compliance: Managing software licensing costs, compliance, and vendor relationships for multi-domain EDA tools /li liData Management Security: Ensuring security for sensitive design data and managing IP (Intellectual Property) for design reuse across digital,
analog, and power projects /li liTest Facility Management and Safety: Ensuring that the test facility supports multi-domain silicon validation and demonstration needs (digital, analog, power), optimizing lab utilization and guaranteeing safety standards including high-voltage compliance /li liTechnical Roadmap Support: Support the Foundation Management in defining technical roadmaps and resource allocation to ensure infrastructure enables multi-domain silicon demonstration objectives from architecture through tape-out and validation /li liMethodology Governance: Establish and maintain common design methodologies and best practices across research groups in all semiconductor domains to ensure efficient IP reuse and design optimization /li liCollaboration Infrastructure Management: Establishing and managing shared access policies for university and industry partners, including remote access to tools and computing resources, IP protection frameworks, and multi-party project coordination /li liTechnology Scouting and Assessment: Continuously monitoring emerging technologies, tools, and methodologies across digital, analog, and power domains to identify potential enablers for research projects, evaluating their applicability and coordinating pilot implementations /li liTechnical Relations with Foundries: Building and maintaining strategic relationships with foundry partners, technology providers to ensure access to cutting-edge processes for all semiconductor domains /li liProactive Research Support: Support the Research Groups in their multi-domain silicon development projects in a proactive manner, leveraging deep semiconductor experience to ensure common approaches, methodology alignment, and resource optimization /li /ul #J-18808-Ljbffr