27 ott - Bologna
VisLab (an Ambarella Inc.
VisLab, an Ambarella Inc. company, in Parma, Italy, seeks a Sr. ASIC Design Engineer to develop micro-architecture for a next-generation computer vision processor and to implement Verilog/SystemVerilog modules for cutting-edge SOCs.
Prima di candidarsi per questo ruolo, la preghiamo di leggere le seguenti informazioni su questa possibilità, riportate di seguito.
The ideal candidate holds a Master’s in Electrical Engineering with up to 4 years of experience and has a strong background in VLSI/ASIC design, design verification, and scripting (Python/Perl). xlwpduy Knowledge in image/video processing and ML is a plus.
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