Chip Design Engineer, Nitro Team
Pubblicato il 27-10-2026 - Amazon in Padova
Annapurna Labs, an Amazon team, designs and delivers high-end, custom silicon at the heart of AWS. Our chips don't just support the cloud; they define it. From Trainium, the purpose-built ML accelerator driving the next wave of AI innovation, to Graviton, the Arm-based server processor redefining price-performance for compute workloads, to Nitro, the advanced network and cloud management controller that underpins every AWS instance — Annapurna's products set the standard for the industry.
We're looking for a talented Chip Design Engineer to join our Nitro team in Tel Aviv and help shape what comes next.
What you'll do:
Take an active, hands-on role in developing the next generation of the Nitro platform
Own critical IP blocks end-to-end — from architecture through tape-out
Collaborate with a world-class, fast-moving design team and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries
If you want to build silicon that leads the cloud world, this is where it happens.
Key job responsibilities
As a Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.
Basic Qualifications
B.Sc. in Electrical Engineering/Computer Engineering
5+ years of experience in Chip Design
Experience working with data paths
Preferred Qualifications
Bachelor's degree in computer science or equivalent
Experience with large scale IPs (Millions of gates)
Experience with a full design cycle – RTL/Verification/Synthesis and timing closure/CDC/ Lint.
Experience with Networking layers
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