Low-bitwidth Numerics for HW-Accel. Digital & Image Signal Processing
Pubblicato il 29-10-2026 - Kineton in Napoli
I moderni kernel computazionali, come DSP/ISP e Deep Learning, non richiedono la vasta precisione della virgola mobile IEEE 754. I recenti sforzi dei grandi player industriali
sono confluiti in MX, una rappresentazione numerica in virgola mobile a bassa larghezza, fino a 4-6 bit, riducendo il sovraccarico hardware nelle moderne GPU e negli acceleratori
tensoriali e neurali.
Questa tesi esplorerà i trade-off nell’implementazione dell’aritmetica MX e validerà l’hardware progettato nelle applicazioni DSP/ISP e Vision Artificiale, confrontandola con alternative a virgola fissa e virgola mobile.
Argomento principale:
Fixed-point and Micro-scaling (MX)
Digital Signal Processing (DSP) / Image Signal Processing (ISP)
Requisiti di base:
Ingegneria Informatica, Elettronica, dell’Automazione, delle Telecomunicazioni o corsi affini.
Conoscenza dei sistemi digitali e digital signal processing (DSP)
Conoscenza con linguaggi hardware Descrizione (VHDL e/o Verilog)
Familiarità con la rappresentazione numerica in floating-point
Sede: Napoli
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Modern computational kernels,
such as DSP/ISP and Deep Learning, do not require the full-range precision of IEEE 754 floating-point. Recent industry efforts have converged
towards MX, a low-bitwidth floating-point numerical representation, down to 4-6 bits, reducing hardware overhead in modern GPUs and tensor/neural accelerators.
This thesis will explore the trade-offs of implementing MX arithmetic and validate the designed hardware on DSP/ISP and Artificial Vision applications, and compare to fixed-point and floating-point alternatives.
Main topic:
Fixed-point and Micro-scaling (MX)
Digital Signal Processing (DSP) / Image Signal Processing (ISP)
Requirements/course of study:
Computer engineering, electronic engineering, telecommunication engineering or similar
Knowledge of digital systems and digital signal processing (DSP)
Knowledge of hardware description languages (VHDL and/or Verilog)
Familiarity with the floating-point numerical representation
Location: Naples