Senior ASIC Design Engineer
VisLab (an Ambarella Inc. company) in Parma, Italy, is seeking a Sr. ASIC Design Engineer to help deliver a next‐generation computer vision processor.
You will design and implement Verilog/SystemVerilog modules for SOCs—image processing logic, vector processors, and device/memory controllers—and drive design integration, synthesis, timing closure and power optimization. Collaborate with a cross‐functional team, contribute to front‐end methodologies and tool flows, and develop a robust, scalable
You will design and implement Verilog/SystemVerilog modules for SOCs—image processing logic, vector processors, and device/memory controllers—and drive design integration, synthesis, timing closure and power optimization. Collaborate with a cross‐functional team, contribute to front‐end methodologies and tool flows, and develop a robust, scalable