Fpga/Asic Design Engineer — Hdl & Verification
Avaneidi in Lombardia is seeking an FPGA/ASIC Hardware Engineer to design, simulate, and verify digital circuits for high-performance FPGA and ASIC solutions.È pronto/a a candidarsi? Si assicuri di aver compreso tutte le responsabilità e i compiti associati a questo ruolo prima di procedere.You will work with software teams to integrate hardware blocks into products. xysqume Candidates should have HDL experience, strong timing analysis, and hands-on with Vivado/Quartus.The role emphasizes fast-paced collaboration and rigorous verification using testbenches and UVM.#J-18808-Ljbffr