Senior staff engineer radio frequency design (f/m/div)
Join our international RF and mixed-signal design team and drive the development of next-generation Frequency Synthesizers for cutting-edge semiconductor solutions. In this role, you will combine deep analog and RF expertise with digital-assisted design approaches, working closely with system architects, digital designers and validation experts from concept to silicon.
Your role
Key responsibilities in your new role
- PLL Concept & Architecture: Define and evaluate RF Digital PLL concepts (e.g., Fractional-N, ADPLL, Sub-sampling PLLs) and architectures tailored for high-frequency wireless applications
- Modeling & Noise Budgets: Develop high-level behavioral models (e.g., MATLAB, Simulink, Verilog-A) to analyze and optimize RF PLL loop dynamics, jitter, spurs,
and stringent phase noise performance.
- Circuit Design & Implementation: Translate concepts into high-performance RF and mixed-signal circuits, focusing on critical blocks such as VCOs/DCOs, high-speed frequency dividers (prescalers), Phase-Frequency Detectors, and Charge Pumps, TDC, DTC
- Digitally-Assisted RF Calibration: Architect and verify digital calibration algorithms for PLL (e.g., spur mitigation, and mismatch compensation, TDC, DTC calibrations) to enhance RF performance
- System Partitioning: Partner closely with system architects, digital, and RF frontend te
Your role
Key responsibilities in your new role
- PLL Concept & Architecture: Define and evaluate RF Digital PLL concepts (e.g., Fractional-N, ADPLL, Sub-sampling PLLs) and architectures tailored for high-frequency wireless applications
- Modeling & Noise Budgets: Develop high-level behavioral models (e.g., MATLAB, Simulink, Verilog-A) to analyze and optimize RF PLL loop dynamics, jitter, spurs,
and stringent phase noise performance.
- Circuit Design & Implementation: Translate concepts into high-performance RF and mixed-signal circuits, focusing on critical blocks such as VCOs/DCOs, high-speed frequency dividers (prescalers), Phase-Frequency Detectors, and Charge Pumps, TDC, DTC
- Digitally-Assisted RF Calibration: Architect and verify digital calibration algorithms for PLL (e.g., spur mitigation, and mismatch compensation, TDC, DTC calibrations) to enhance RF performance
- System Partitioning: Partner closely with system architects, digital, and RF frontend te