FPGA/ASIC Design Engineer — HDL
Avaneidi in Lombardia is seeking an FPGA/ASIC Hardware Engineer to design, simulate, and verify digital circuits for high-performance FPGA and ASIC solutions. You will work with software teams to integrate hardware blocks into products.
Candidates should have HDL experience, strong timing analysis, and hands-on with Vivado/Quartus. The role emphasizes fast-paced collaboration and rigorous verification using testbenches and UVM.
Candidates should have HDL experience, strong timing analysis, and hands-on with Vivado/Quartus. The role emphasizes fast-paced collaboration and rigorous verification using testbenches and UVM.