SoC Physical Design Engineer for Next-Gen ASICs
Nokia in Umbria, Italy seeks a SoC Physical Design Engineer to drive floorplanning, placement, routing and timing closure for 3/5/7nm ASICs. You will optimize power, performance and area within a hardware/RTL team, translating designs into silicon and advancing PD methodologies.
Collaborate with RTL designers, run IV/DT verifications, and develop automation scripts using TCL/Python to streamline Synthesis through GDSII for multi-project IPs.
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Collaborate with RTL designers, run IV/DT verifications, and develop automation scripts using TCL/Python to streamline Synthesis through GDSII for multi-project IPs.
#J-18808-Ljbffr