Senior Digital Verification Engineer
Overview
As Digital Verification Engineer, you will verify digital and mixed-signal ASICs using modern verification methods, leading EDA tools, and AI-assisted workflows. You will build scalable verification environments and push first-silicon quality, contributing across the product lifecycle. You’ll collaborate with a globally distributed team to shape innovative semiconductor solutions and drive reliability and performance. This role offers opportunities to impact product quality, engineering excellence, and cross-functional collaboration in a cutting-edge environment.
Retribuzione / Benefits company performance-related premio
additional benefits
Responsabilità Design scalable, reusable verification environments for complex ICs to accelerate first silicon bring-up
Apply advanced verification methodologies (functional, formal) to validate digital designs and improve reliability
Collaborate with engineers across international locations in a distributed development setup
Participate from concept to production across the full product lifecycle
Document and improve verification processes and best practices to raise efficiency and knowledge sharing
Requisiti fondamentali 5+ years of professional ASIC/SoC verification experience
Expertise in UVM, formal verification, and directed verification
Strong understanding of digital circuit design (VHDL/Verilog, Digital IP)
Experience with verification environments for mixed-signal/SoC designs
Hands-on with state-of-the-art simulation, verification, and EDA tools
Analog/mixed-signal modeling (wreal, MATLAB/Simulink, SystemC)
Power-aware verification and UPF methodology
Scripting/automation in Python or Tcl
Interest in applying AI-assisted workflows to verification
Proficient English (C1)
passion for technology and quality
curiosity and creativity
proactive mindset
UVM
formal verification
directed verification
As Digital Verification Engineer, you will verify digital and mixed-signal ASICs using modern verification methods, leading EDA tools, and AI-assisted workflows. You will build scalable verification environments and push first-silicon quality, contributing across the product lifecycle. You’ll collaborate with a globally distributed team to shape innovative semiconductor solutions and drive reliability and performance. This role offers opportunities to impact product quality, engineering excellence, and cross-functional collaboration in a cutting-edge environment.
Retribuzione / Benefits company performance-related premio
additional benefits
Responsabilità Design scalable, reusable verification environments for complex ICs to accelerate first silicon bring-up
Apply advanced verification methodologies (functional, formal) to validate digital designs and improve reliability
Collaborate with engineers across international locations in a distributed development setup
Participate from concept to production across the full product lifecycle
Document and improve verification processes and best practices to raise efficiency and knowledge sharing
Requisiti fondamentali 5+ years of professional ASIC/SoC verification experience
Expertise in UVM, formal verification, and directed verification
Strong understanding of digital circuit design (VHDL/Verilog, Digital IP)
Experience with verification environments for mixed-signal/SoC designs
Hands-on with state-of-the-art simulation, verification, and EDA tools
Analog/mixed-signal modeling (wreal, MATLAB/Simulink, SystemC)
Power-aware verification and UPF methodology
Scripting/automation in Python or Tcl
Interest in applying AI-assisted workflows to verification
Proficient English (C1)
passion for technology and quality
curiosity and creativity
proactive mindset
UVM
formal verification
directed verification