LLVM Compiler Toolchain for Vector Processors Targeting AI Applications in Space and Defence
Organisation/Company ALMA MATER STUDIORUM - UNIVERSITA' DI BOLOGNA - - DIPARTIMENTO DI INGEGNERIA DELL'ENERGIA ELETTRICA E DELL'INFORMAZIONE "GUGLIELMO MARCONI" Research Field Engineering » Electronic engineering Researcher Profile Recognised Researcher (R2) Leading Researcher (R4) First Stage Researcher (R1) Established Researcher (R3) Application Deadline 4 Nov 2026 - 23:59 (UTC) Country Italy Type of Contract To be defined Job Status Not Applicable Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No
Offer Description
AI workloads on space and defence platforms, such as on-board satellite image processing, autonomous navigation and multi-sensor fusion, must run under tight power, reliability and certification constraints, which favour compact,
programmable vector processors over fixed-function accelerators. Their efficiency depends largely on the compiler. This Incarico di Ricerca, aligned with the activity of the ARCHYTAS project, focuses on the LLVM compiler infrastructure for vector processors based on the RISC-V Vector (RVV) extension. Activities include: backend support for custom vector instructions and low-precision data types (e.g., FP8, INT8/INT4); vectorization and tiling of AI kernels (matrix multiplication, convolution, attention); integration with MLIR-based flows; evaluation on RTL/FPGA platforms with representative space and defence workloads.
- Italy
Eligibility of fellows: country/ies of residence:
- All
Eligibility of fellows: nationality/ies:
Offer Description
AI workloads on space and defence platforms, such as on-board satellite image processing, autonomous navigation and multi-sensor fusion, must run under tight power, reliability and certification constraints, which favour compact,
programmable vector processors over fixed-function accelerators. Their efficiency depends largely on the compiler. This Incarico di Ricerca, aligned with the activity of the ARCHYTAS project, focuses on the LLVM compiler infrastructure for vector processors based on the RISC-V Vector (RVV) extension. Activities include: backend support for custom vector instructions and low-precision data types (e.g., FP8, INT8/INT4); vectorization and tiling of AI kernels (matrix multiplication, convolution, attention); integration with MLIR-based flows; evaluation on RTL/FPGA platforms with representative space and defence workloads.
- Italy
Eligibility of fellows: country/ies of residence:
- All
Eligibility of fellows: nationality/ies: