Senior Asic Design Engineer
VisLab, an Ambarella Inc. company, in Parma, Italy, seeks a Sr.
ASIC Design Engineer to develop micro-architecture for a next-generation computer vision processor and to implement Verilog/SystemVerilog modules for cutting-edge SOCs.
The ideal candidate holds a Master's in Electrical Engineering with up to 4 years of experience and has a strong background in VLSI/ASIC design, design verification, and scripting (Python/Perl).
Knowledge in image/video processing and ML is a plus.
#J-*-Ljbffr
ASIC Design Engineer to develop micro-architecture for a next-generation computer vision processor and to implement Verilog/SystemVerilog modules for cutting-edge SOCs.
The ideal candidate holds a Master's in Electrical Engineering with up to 4 years of experience and has a strong background in VLSI/ASIC design, design verification, and scripting (Python/Perl).
Knowledge in image/video processing and ML is a plus.
#J-*-Ljbffr