Senior Digital Design Engineer
NXP Semiconductors NV in Varese, Lombardy, Italy, is seeking a Senior Digital Design Engineer to design RTL blocks and subsystems using SystemVerilog/Verilog.
You will work with architects and verification teams to optimize performance, power and area while ensuring safety-compliant digital designs.
The role requires 7+ years in digital IC design, strong RTL skills, and experience with synthesis, timing constraints, and mixed-signal contexts.
#J-*-Ljbffr
You will work with architects and verification teams to optimize performance, power and area while ensuring safety-compliant digital designs.
The role requires 7+ years in digital IC design, strong RTL skills, and experience with synthesis, timing constraints, and mixed-signal contexts.
#J-*-Ljbffr