Principal Verification Engineer

Pubblicato il 06-11-2026 · Onsemi · Bardi

Seeking a Principal Verification Engineer to design and execute verification strategies for integrated circuits, focusing on block-level and SoC-level verification using SystemVerilog, UVM, and formal methods.
Max. 8 MB. Formati Accettati: PDF, RTF, DOC, DOCX, ODT.