Senior Asic Design Engineer
VisLab (an Ambarella Inc. company) in Parma, Italy seeks a Sr.
ASIC Design Engineer to develop micro?architecture for a next?gen computer vision processor and implement modules in Verilog/SystemVerilog for SOCs.
You will optimize timing, area and power while advancing front?end methodologies and tool flows.
The role requires a Master's in Electrical Engineering and 0–4 years of relevant experience with strong HDL skills and scripting ability in Python or Perl.
#J-*-Ljbffr
ASIC Design Engineer to develop micro?architecture for a next?gen computer vision processor and implement modules in Verilog/SystemVerilog for SOCs.
You will optimize timing, area and power while advancing front?end methodologies and tool flows.
The role requires a Master's in Electrical Engineering and 0–4 years of relevant experience with strong HDL skills and scripting ability in Python or Perl.
#J-*-Ljbffr