Senior Digital Design Engineer — RTL/Verilog, Bonus
Renesas in Catania is seeking a Senior Digital Design Engineer to contribute to next-generation power management solutions for AI, Cloud and Data Center applications. You will design digital blocks in Verilog/SystemVerilog and work with cross-functional teams to deliver robust RTL.
The role offers a yearly salary range of €37,000 to €50,000 with potential premio; based in Catania, it requires good English communication and a collaborative mindset.
The role offers a yearly salary range of €37,000 to €50,000 with potential premio; based in Catania, it requires good English communication and a collaborative mindset.