SoC Physical Design Engineer for Next-Gen ASICs
Nokia in Umbria, Italy seeks a SoC Physical Design Engineer to drive floorplanning, placement, routing and timing closure for 3/5/7nm ASICs.
L'esperienza richiesta ai candidati, così come le competenze e le qualifiche aggiuntive necessarie per questo lavoro, sono elencate di seguito.
You will optimize power, performance and area within a hardware/RTL team, translating designs into silicon and advancing PD methodologies.
Collaborate with RTL designers, run IV/DT verifications, and develop xbvzest automation scripts using TCL/Python to streamline Synthesis through GDSII for multi-project IPs.
L'esperienza richiesta ai candidati, così come le competenze e le qualifiche aggiuntive necessarie per questo lavoro, sono elencate di seguito.
You will optimize power, performance and area within a hardware/RTL team, translating designs into silicon and advancing PD methodologies.
Collaborate with RTL designers, run IV/DT verifications, and develop xbvzest automation scripts using TCL/Python to streamline Synthesis through GDSII for multi-project IPs.