Senior Digital Design Engineer
h3 Senior Digital IC Designer Location: Milan, Italy – NXP Semiconductors /h3 /brp NXP Semiconductors is seeking a Senior Digital IC Designer to contribute to the development of advanced mixed-signal integrated circuits for automotive and industrial electrification applications.
The successful candidate will play a key role in the design, implementation, and integration of digital subsystems, working closely with architects, verification engineers, and multidisciplinary development teams.
/p /brh3 Key Responsibilities /h3 /brh3 Digital Design and Implementation /h3 /brul /brli Develop RTL designs for complex digital blocks and subsystems using System Verilog/Verilog.
/li /brli Contribute to digital architecture definition together with senior designers and system architects.
/li /brli Analyze design trade-offs related to performance, power consumption, area, safety, and testability.
/li /brli Implement robust clocking, reset, and power management strategies.
/li /brli Support IP integration and subsystem-level development.
/li /br /ul /brh3 Design Quality and Verification Support /h3 /brul /brli Perform RTL verification activities, including simulation, lint, CDC, and synthesis checks.
/li /brli Collaborate closely with digital verification engineers to ensure specification coverage and design quality.
/li /brli Support timing closure and implementation activities.
/li /brli Participate in design reviews and contribute to sign-off readiness.
/li /brli Support silicon bring-up, debugging, characterization, and root-cause analysis.
/li /br /ul /brh3 Mixed-Signal and Product Development Collaboration /h3 /brul /brli Work effectively within mixed-signal project teams including analog designers, verification engineers, system architects, and application engineers.
/li /brli Contribute to requirements definition and technical feasibility analysis.
/li /brli Support multiple development phases from concept through production release.
/li /brli Promote reuse of digital IPs and design methodologies.
/li /br /ul /brh3 Functional Safety and Quality /h3 /brul /brli Contribute to the implementation of safety mechanisms in compliance with automotive standards.
/li /brli Support functional safety analysis and reviews.
/li /brli Follow established development processes and quality standards for automotive and industrial products.
/li /br /ul /brh3 Team Contribution /h3 /brul /brli Provide technical support and guidance to less experienced engineers.
/li /brli Share knowledge, methodologies, and best practices within the team.
/li /brli Collaborate effectively across international RD sites.
/li /br /ul /brh3 Required Skills /h3 /brul /brli Master's degree in Electrical Engineering, Electronics Engineering, or equivalent.
/li /brli Minimum 7 years of experience in digital IC design.
/li /brli Strong experience in RTL development using System Verilog/Verilog.
/li /brli Experience with synthesis, timing constraints, and digital implementation flows.
/li /brli Understanding of CDC, reset strategies, and low-power design concepts.
/li /brli Familiarity with DFT fundamentals and design-for-test methodologies.
/li /brli Experience working in mixed-signal IC development environments.
/li /brli Knowledge of digital verification methodologies and simulation-based verification.
/li /brli Experience with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA).
/li /brli Fluent written and spoken English.
/li /br /ul /brh3 Preferred Qualifications /h3 /brul /brli Experience in automotive or industrial semiconductor products.
/li /brli Familiarity with automotive functional safety concepts (ISO *****).
/li /brli Experience with electrification applications such as Battery Management Systems (BMS), High Voltage Gate Drivers, or Power Management ICs.
/li /brli Knowledge of digital signal processing techniques.
/li /brli Experience supporting first silicon bring-up and product qualification activities.
/li /brli Experience working within geographically distributed development teams.
/li /br /ul /brp NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.
As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually.
This range is intended as a guideline.
Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs.
This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria).
Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.
More information about NXP in Italy... /p /brp Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind.
We have programs in place focused on diversity, inclusion and equality.
Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities.
Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited.
Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise.
/p #J-*****-Ljbffr
The successful candidate will play a key role in the design, implementation, and integration of digital subsystems, working closely with architects, verification engineers, and multidisciplinary development teams.
/p /brh3 Key Responsibilities /h3 /brh3 Digital Design and Implementation /h3 /brul /brli Develop RTL designs for complex digital blocks and subsystems using System Verilog/Verilog.
/li /brli Contribute to digital architecture definition together with senior designers and system architects.
/li /brli Analyze design trade-offs related to performance, power consumption, area, safety, and testability.
/li /brli Implement robust clocking, reset, and power management strategies.
/li /brli Support IP integration and subsystem-level development.
/li /br /ul /brh3 Design Quality and Verification Support /h3 /brul /brli Perform RTL verification activities, including simulation, lint, CDC, and synthesis checks.
/li /brli Collaborate closely with digital verification engineers to ensure specification coverage and design quality.
/li /brli Support timing closure and implementation activities.
/li /brli Participate in design reviews and contribute to sign-off readiness.
/li /brli Support silicon bring-up, debugging, characterization, and root-cause analysis.
/li /br /ul /brh3 Mixed-Signal and Product Development Collaboration /h3 /brul /brli Work effectively within mixed-signal project teams including analog designers, verification engineers, system architects, and application engineers.
/li /brli Contribute to requirements definition and technical feasibility analysis.
/li /brli Support multiple development phases from concept through production release.
/li /brli Promote reuse of digital IPs and design methodologies.
/li /br /ul /brh3 Functional Safety and Quality /h3 /brul /brli Contribute to the implementation of safety mechanisms in compliance with automotive standards.
/li /brli Support functional safety analysis and reviews.
/li /brli Follow established development processes and quality standards for automotive and industrial products.
/li /br /ul /brh3 Team Contribution /h3 /brul /brli Provide technical support and guidance to less experienced engineers.
/li /brli Share knowledge, methodologies, and best practices within the team.
/li /brli Collaborate effectively across international RD sites.
/li /br /ul /brh3 Required Skills /h3 /brul /brli Master's degree in Electrical Engineering, Electronics Engineering, or equivalent.
/li /brli Minimum 7 years of experience in digital IC design.
/li /brli Strong experience in RTL development using System Verilog/Verilog.
/li /brli Experience with synthesis, timing constraints, and digital implementation flows.
/li /brli Understanding of CDC, reset strategies, and low-power design concepts.
/li /brli Familiarity with DFT fundamentals and design-for-test methodologies.
/li /brli Experience working in mixed-signal IC development environments.
/li /brli Knowledge of digital verification methodologies and simulation-based verification.
/li /brli Experience with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA).
/li /brli Fluent written and spoken English.
/li /br /ul /brh3 Preferred Qualifications /h3 /brul /brli Experience in automotive or industrial semiconductor products.
/li /brli Familiarity with automotive functional safety concepts (ISO *****).
/li /brli Experience with electrification applications such as Battery Management Systems (BMS), High Voltage Gate Drivers, or Power Management ICs.
/li /brli Knowledge of digital signal processing techniques.
/li /brli Experience supporting first silicon bring-up and product qualification activities.
/li /brli Experience working within geographically distributed development teams.
/li /br /ul /brp NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.
As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually.
This range is intended as a guideline.
Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs.
This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria).
Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.
More information about NXP in Italy... /p /brp Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind.
We have programs in place focused on diversity, inclusion and equality.
Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities.
Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited.
Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise.
/p #J-*****-Ljbffr