Design / DFT Director (NVE Engineering)
Overview
Senior leadership role shaping Micron’s NAND DFT strategy for cutting-edge memory products. You define the DFT vision, roadmaps, and governance, driving architecture, verification, and sign-off from concept to mass production. You collaborate across Design, Test, Manufacturing, and Quality to improve yield, test time, and reliability, while scaling AI-enabled test diagnostics and silicon learning. This role blends deep semiconductor expertise with people leadership to build a high-performing, global DFT organization.
Retribuzione / Benefits
- meal vouchers
- corporate welfare
- remote working days
- supplementary health insurance
- life coverage
- Employee Assistance Program
Responsabilità
- Define and lead the global NAND DFT vision, strategy, and technical roadmap across programs and technology generations
- Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out
- Collaborate with Design, Product Engineering, Test, Probe, Failure Analysis, Quality, Technology Development, and Manufacturing to optimize quality, yield, test time, cost, and time-to-market
- Drive reusable methodologies, automation, and DFT/design-for-debug innovation; improve simulation-to-silicon correlation and diagnostics
- Build and mentor a high-performing global DFT organization; manage priorities,
resources, and talent development across complex programs
- Lead AI Enablement and Productivity initiatives; deploy AI/ML strategies for test-pattern optimization, fault diagnosis, and yield prediction
- Establish AI-enabled DFT, diagnostic, and analytics workflows with measurable gains in debugging efficiency and engineering productivity
- Communicate strategy, plans, risks, and results to senior partners while maintaining technical depth and inclusive culture
Requisiti fondamentali
- M.S. in Electrical Engineering (or related field)
- Significant semiconductor design, DFT, product test, or silicon validation experience
- Proven ability to define strategy and deliver complex products from concept to tape-out and manufacturing
- Deep knowledge of NAND design, DFT principles, test architecture, coverage analysis, and silicon debugging
- Proven people leadership and cross-functional influence in a global environment
- Solid understanding of AI/ML and data-analytics as applied to semiconductor design, test, or manufacturing
- Proficiency with scripting/programming languages (Python, C/C++) and engineering automation
- executive communication
- leadership and mentoring
- cross-functional collaboration
- NAND design
- DFT principles
- test architecture
Senior leadership role shaping Micron’s NAND DFT strategy for cutting-edge memory products. You define the DFT vision, roadmaps, and governance, driving architecture, verification, and sign-off from concept to mass production. You collaborate across Design, Test, Manufacturing, and Quality to improve yield, test time, and reliability, while scaling AI-enabled test diagnostics and silicon learning. This role blends deep semiconductor expertise with people leadership to build a high-performing, global DFT organization.
Retribuzione / Benefits
- meal vouchers
- corporate welfare
- remote working days
- supplementary health insurance
- life coverage
- Employee Assistance Program
Responsabilità
- Define and lead the global NAND DFT vision, strategy, and technical roadmap across programs and technology generations
- Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out
- Collaborate with Design, Product Engineering, Test, Probe, Failure Analysis, Quality, Technology Development, and Manufacturing to optimize quality, yield, test time, cost, and time-to-market
- Drive reusable methodologies, automation, and DFT/design-for-debug innovation; improve simulation-to-silicon correlation and diagnostics
- Build and mentor a high-performing global DFT organization; manage priorities,
resources, and talent development across complex programs
- Lead AI Enablement and Productivity initiatives; deploy AI/ML strategies for test-pattern optimization, fault diagnosis, and yield prediction
- Establish AI-enabled DFT, diagnostic, and analytics workflows with measurable gains in debugging efficiency and engineering productivity
- Communicate strategy, plans, risks, and results to senior partners while maintaining technical depth and inclusive culture
Requisiti fondamentali
- M.S. in Electrical Engineering (or related field)
- Significant semiconductor design, DFT, product test, or silicon validation experience
- Proven ability to define strategy and deliver complex products from concept to tape-out and manufacturing
- Deep knowledge of NAND design, DFT principles, test architecture, coverage analysis, and silicon debugging
- Proven people leadership and cross-functional influence in a global environment
- Solid understanding of AI/ML and data-analytics as applied to semiconductor design, test, or manufacturing
- Proficiency with scripting/programming languages (Python, C/C++) and engineering automation
- executive communication
- leadership and mentoring
- cross-functional collaboration
- NAND design
- DFT principles
- test architecture