Design / DFT Director (NVE Engineering)
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Massimizzi le sue possibilità di successo assicurandosi che il suo CV e le sue competenze corrispondano ai requisiti di questa posizione.
Department Introduction
The Non-Volatile NAND Design Engineering organization is responsible for the architecture, design, integration, and optimization of analog, digital, mixed-signal, and test solutions enabling advanced NAND Flash memory products. Close collaboration across global design, technology, product, test, and manufacturing teams ensures scalable, manufacturable, reliable, and cost-effective products across technology generations.
Position Overview
We are seeking an expert and innovative Director of NAND Design for Test (DFT) to lead the global DFT strategy, architecture, and execution for advanced NAND Flash products at Micron Semiconductor Italia. In this senior leadership role, you will define the DFT vision and technical roadmap, owning architecture, methodology, integration, verification, coverage closure, and build sign-off from early product definition through silicon initialization, validation, and mass production. You will combine deep semiconductor and DFT expertise with strong interpersonal and people leadership, partnering with Design, Product Engineering, Test, Probe, Quality, Failure Analysis, Technology Development, and Manufacturing to improve product quality, yield, cost, test time, reliability, and time to market. AI, machine learning, and data analytics are a core pillar of this role.
You will lead adoption across the DFT organization and transform the delivery of testability, diagnostics, and silicon learning at scale. You will build and scale a high-performing distributed and international group.
Responsibilities
Define and lead the global NAND DFT vision, strategy, and technical roadmap across product programs and technology generations; anticipate future requirements and establish scalable architectures, methodologies, technical priorities, success metrics, and governance aligned with quality, cost, performance, and schedule objectives.
Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out; lead scalable testability, diagnostic, design-for-debug, and embedded test solutions across digital logic and custom circuits, ensuring predictable delivery and clear coverage, test-time, area, power, quality, and execution targets.
Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs; work with Product Engineering, Test, Probe, Failure Analysis, Quality, Technology Development, and Manufacturing through silicon bring-up, qualification, and high-volume production to achieve quality, coverage, yield, reliability, test-time, cost, and time-to-market objectives.
Drive reusable methodologies, automation,
and DFT and design-for-debug innovation; strengthen simulation-to-silicon correlation, diagnostics, and root-cause resolution, with measurable improvements in debug efficiency, silicon learning, test quality, test time, yield learning, product cost, and time to market.
Build, develop, and inspire a high-performing global DFT organization; develop managers and senior technical leaders through mentoring, talent development, performance management, succession planning, and career growth. Allocate priorities and resources across complex programs, communicate strategy, plans, decisions, risks, and results to senior partners, and sustain technical depth, AI and data skills, leadership capability, engagement, and retention within an inclusive, high-trust engineering culture.
AI Enablement and Productivity
AI, machine learning, and data analytics are a core leadership responsibility, not an optional productivity tool. The Director will define and lead the AI/ML strategy for DFT and scale adoption across the global organization, with measurable engineering and product outcomes:
Deploy data-driven and AI-assisted solutions for test-pattern and test-flow optimization, fail diagnosis and root-cause analysis, yield prediction, coverage analytics, and test-time reduction.
Establish reusable AI-enabled DFT, diagnostic, and analytics workflows; measure gains in debug time, test time, yield learning, engineering productivity, quality, and execution speed.
Build AI and data-analytics capabilities across the team and partner across functions to evaluate, adopt, and scale emerging tools and methodologies supporting future NAND technology generations.
Minimum Qualifications
M.S. or Ph.D. in Electrical Engineering, Elect
Massimizzi le sue possibilità di successo assicurandosi che il suo CV e le sue competenze corrispondano ai requisiti di questa posizione.
Department Introduction
The Non-Volatile NAND Design Engineering organization is responsible for the architecture, design, integration, and optimization of analog, digital, mixed-signal, and test solutions enabling advanced NAND Flash memory products. Close collaboration across global design, technology, product, test, and manufacturing teams ensures scalable, manufacturable, reliable, and cost-effective products across technology generations.
Position Overview
We are seeking an expert and innovative Director of NAND Design for Test (DFT) to lead the global DFT strategy, architecture, and execution for advanced NAND Flash products at Micron Semiconductor Italia. In this senior leadership role, you will define the DFT vision and technical roadmap, owning architecture, methodology, integration, verification, coverage closure, and build sign-off from early product definition through silicon initialization, validation, and mass production. You will combine deep semiconductor and DFT expertise with strong interpersonal and people leadership, partnering with Design, Product Engineering, Test, Probe, Quality, Failure Analysis, Technology Development, and Manufacturing to improve product quality, yield, cost, test time, reliability, and time to market. AI, machine learning, and data analytics are a core pillar of this role.
You will lead adoption across the DFT organization and transform the delivery of testability, diagnostics, and silicon learning at scale. You will build and scale a high-performing distributed and international group.
Responsibilities
Define and lead the global NAND DFT vision, strategy, and technical roadmap across product programs and technology generations; anticipate future requirements and establish scalable architectures, methodologies, technical priorities, success metrics, and governance aligned with quality, cost, performance, and schedule objectives.
Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out; lead scalable testability, diagnostic, design-for-debug, and embedded test solutions across digital logic and custom circuits, ensuring predictable delivery and clear coverage, test-time, area, power, quality, and execution targets.
Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs; work with Product Engineering, Test, Probe, Failure Analysis, Quality, Technology Development, and Manufacturing through silicon bring-up, qualification, and high-volume production to achieve quality, coverage, yield, reliability, test-time, cost, and time-to-market objectives.
Drive reusable methodologies, automation,
and DFT and design-for-debug innovation; strengthen simulation-to-silicon correlation, diagnostics, and root-cause resolution, with measurable improvements in debug efficiency, silicon learning, test quality, test time, yield learning, product cost, and time to market.
Build, develop, and inspire a high-performing global DFT organization; develop managers and senior technical leaders through mentoring, talent development, performance management, succession planning, and career growth. Allocate priorities and resources across complex programs, communicate strategy, plans, decisions, risks, and results to senior partners, and sustain technical depth, AI and data skills, leadership capability, engagement, and retention within an inclusive, high-trust engineering culture.
AI Enablement and Productivity
AI, machine learning, and data analytics are a core leadership responsibility, not an optional productivity tool. The Director will define and lead the AI/ML strategy for DFT and scale adoption across the global organization, with measurable engineering and product outcomes:
Deploy data-driven and AI-assisted solutions for test-pattern and test-flow optimization, fail diagnosis and root-cause analysis, yield prediction, coverage analytics, and test-time reduction.
Establish reusable AI-enabled DFT, diagnostic, and analytics workflows; measure gains in debug time, test time, yield learning, engineering productivity, quality, and execution speed.
Build AI and data-analytics capabilities across the team and partner across functions to evaluate, adopt, and scale emerging tools and methodologies supporting future NAND technology generations.
Minimum Qualifications
M.S. or Ph.D. in Electrical Engineering, Elect