Principal Hs Digital Design Engineer
Your tasksTechnical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal So C productsDefine digital subsystem architecturesLead RTL development and integrationDrive design reviews and quality standardsSupport verification and implementation teamsMentor design engineersWho we are looking forMSc or Ph D in Electrical Engineering10+ years digital IC design experienceRTL design (Verilog/System Verilog)High-speed digital IC design