22 set - Casaletto Lodigiano
Ams Italy
ams OSRAM is seeking an experienced engineering leader to architect and drive RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoCs.
The role requires a strong background in RTL design (Verilog/SystemVerilog), CMOS process nodes, and timing analysis across fast interfaces. You will mentor engineers and coordinate architecture reviews in a global R&D; environment.
01 ott - Roma
Rosewood Rome
01 ott - Bologna
Lafarmaciapunto | B
01 ott - Trieste
Lafarmaciapunto | B
01 ott - Trieste
TRIPMARE