30 set - Venezia
Elettrotecnica
In this role you will lead end-to-end ADC design and analog/mixed-signal blocks, collaborating with cross-functional teams to bring high-performance converters to silicon. You'll drive pre- and post-silicon verification, modeling, and architecture decisions that shape product performance and reliability. The position offers the opportunity to mentor engineers, contribute to cutting-edge ADC tech, and influence design methodology across projects.
This role aligns with Infineon's mission to enable green, secure, and efficient energy through advanced semiconductor solutions.
salary aligned with collective agreement location-based compensation performance-based rewards Lead end-to-end ADC design including architecture, circuit implementation, and silicon bring-up for SAR, Pipeline, Sigma-Delta, Flash, or hybrid topologies Design analog/mixed-signal building blocks (OTAs, comparators, DACs, sample-and-hold, references, clocking/bias) with ownership of performance, power, area, and cost Perform pre-silicon verification from transistor to chip level, including Monte Carlo and corner analyses, and post-silicon lab characterization and debugging Develop behavioral/architectural models of ADC/mixed-signal blocks using Python and MATLAB for system-level exploration Collaborate cross-functionally with digital design, physical design,
and CAD teams to ensure successful tape-out and align with customer requirements Mentor junior and mid-level engineers, lead design reviews, and contribute innovative ideas based on state-of-the-art trends in mixed-signal and ADC design 5+ years of hands-on analog and mixed-signal IC design with proven silicon tape-outs and product bring-up Strong expertise in ADC architectures (SAR, Pipeline, Sigma-Delta, Flash, or hybrid) and analog blocks (OTAs, comparators, references, LDOs, switched-capacitor circuits) Solid understanding of mixed-signal design including clock distribution, digital calibration, timing closure, and asynchronous logic Proficiency with EDA tools (Cadence Virtuoso/Spectre, ADE XL, HSPICE or equivalent), full custom IC design flow, and experience with advanced CMOS nodes (130nm–12nm) Python and/or MATLAB/Simulink for automation, scripting, and system-level modeling; knowledge of digital calibration techniques Cross-functional collaboration Mentoring and leadership Innovation and state-of-the-art thinking ADC architectures (SAR, Pipeline, Sigma-Delta, Flash, or hybrid) Analog building blocks (OTAs, comparators, references, LDOs, switched-capacitor circuits) Clock distribution and timing closure Senior Staff Engineer Analog Mixed-Signal Design (f/m/div) venezia, veneto, it
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